1. Field of the Disclosure
The disclosure relates generally to memories, and more specifically to testing of non-volatile memory devices.
2. Description of the Related Art
Some types of non-volatile memories (NVMs) cells are programmed and erased by applying specific program bias voltages and erase bias voltages, respectively, for which there is generally a limit as to how many times these operations can be performed. Also a common NVM memory type, generally referred to as flash memory, includes many NVM memory cells (a block) that are erased simultaneously. Due to performance variations, for a given set of erase bias voltages some NVM memory cells of a block will be erased, e.g., placed in an erased state, faster than other NVM memory cells of the block. Thus, because the duration of an erase cycle is selected to erase all cells of an NVM block, those NVM memory cells that are erased more quickly than other memory cells of the same block will continue to be subjected to erase conditions, e.g., application of the erase bias voltages, unnecessarily, while slower NVM memory cells are still being erased. The bits that take longer to erase for a given set of erase bias voltages are referred to as slow bits.
Therefore, faster to erase NVM bits can become over-erased, which can result in memory cells that exhibit undesirable characteristics, such as excessive current leakage. To address such issues, faster to erase memory cells can be subject to one or more programming pulses, referred to as soft program pulses, to bring them into a desired statistical distribution of erased memory cells and to overcome the problems associated with over-erase. This programming is referred to as soft programming. Soft programming typically takes a relatively long time since it is done per address and with a low program bias. As more cells are required to be soft programmed, the increasing duration of soft programming may eventually cause the embedded erase operation to fail to complete within the specified maximum time. Also, over time, after perhaps tens of thousands of program/erase cycles, some NVM memory cells can become weak or slow to erase. These latent weak memory cells are very difficult to detect until they actually become weak or slow to erase. Thus, it is not uncommon for slow-to-erase memory cells to pass production testing, but become evident well after the device has been placed in an end product. For example, such a slow-to-erase bit can result in the NVM control logic to extending erase time of the entire erase block that includes the now slow bit, which in turn is likely to cause an over-erased distribution of the block's memory cells after the erase operation, hence significantly slowing down the following soft program operation. Eventually such a slow-to-erase bit will cause an embedded erase operation to fail.
The use of the same reference symbols in different drawings indicates similar or identical items.